Cut and paste this URL to share the unmodified register and value:
https://regviz.com/r/Microchip Technology/ATSAME51J19A/SERCOM0/SPIS/INTENCLR#0x0
SPIS Interrupt Enable Clear
Data Register Empty Interrupt Disable
Transmit Complete Interrupt Disable
Receive Complete Interrupt Disable
Slave Select Low Interrupt Disable
Combined Error Interrupt Disable
https://github.com/cmsis-svd/cmsis-svd-data